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Silicon Labs /BGM240PA32VNA /HFXO0_S /STATUS

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Interpret as STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RDY)RDY 0 (COREBIASOPTRDY)COREBIASOPTRDY 0 (PRSRDY)PRSRDY 0 (BUFOUTRDY)BUFOUTRDY 0 (BUFOUTFROZEN)BUFOUTFROZEN 0 (ENS)ENS 0 (HWREQ)HWREQ 0 (ISWARM)ISWARM 0 (PRSHWREQ)PRSHWREQ 0 (BUFOUTHWREQ)BUFOUTHWREQ 0 (SYNCBUSY)SYNCBUSY 0 (UNLOCKED)LOCK

LOCK=UNLOCKED

Description

No Description

Fields

RDY

Ready Status
COREBIASOPTRDY

Core Bias Optimization Ready
PRSRDY

PRS Ready Status
BUFOUTRDY

BUFOUT Ready Status
BUFOUTFROZEN

BUFOUT Frozen
ENS

Enabled Status
HWREQ

Oscillator Requested by Digital Clock
ISWARM

Oscillator Is Kept Warm
PRSHWREQ

Oscillator Requested by PRS Request
BUFOUTHWREQ

Oscillator Requested by BUFOUT Request
SYNCBUSY

Sync Busy
LOCK

Configuration Lock Status

0 (UNLOCKED): Configuration lock is unlocked

1 (LOCKED): Configuration lock is locked

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data